Architecture level optimization of 3-dimensional tree-based FPGA
نویسندگان
چکیده
منابع مشابه
Architecture level optimization of 3-dimensional tree-based FPGA
We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. The vertical partitionin...
متن کاملPyhsical Design Exploration of 3D Tree-based FPGA Architecture
An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a mult-dimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silic...
متن کاملA Framework for Architecture-Level Exploration of 3-D FPGA Platforms
Interconnection structures in FPGAs increasingly contribute more to the delay and power consumption. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have not been sufficiently explored yet. This paper introduces a novel 3-D FPGA, wher...
متن کاملPerformance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA
A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multilevel network with the logic blocks placed at different Tree levels using ButterflyFat-Tree network topology. 2D physical layout development of a Tree-based multilevel interconne...
متن کاملFPGA-Based Architecture for Computing Testors
Irreducible testors (also named typical testors) are a useful tool for feature selection in supervised classification problems with mixed incomplete data. However, the complexity of computing all irreducible testors of a training matrix has an exponential growth with respect to the number of columns in the matrix. For this reason different approaches like heuristic algorithms, parallel and dist...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Microelectronics Journal
سال: 2014
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2013.12.011